SH7263 Datasheet, PDF (1442/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
Image for Display in
Memory
(X-Resolution × Y-
Resolution)
LCD Module
(X-Resolution × Number of Colors for
Y-Resolution) Display
Number of
Column
Address Bits of Burst Length of
SDRAM
LCDC (LDSMR*)
64 × 128
128 × 64
Monochrome 1 bpp
8 bits
⎯
9 bits
⎯
10 bits
⎯
2 bpp
8 bits
⎯
9 bits
⎯
10 bits
⎯
4 bpp
(packed)
8 bits
Not more than 16
bursts
9 bits
⎯
10 bits
⎯
4 bpp
(unpacked)
8 bits
9 bits
Not more than 8 bursts
Not more than 16
bursts
10 bits
⎯
6 bpp
8 bits
Not more than 8 bursts
9 bits
Not more than 16
bursts
10 bits
⎯
Color
4 bpp
8 bits
Not more than 16
bursts
(packed)
9 bits
⎯
10 bits
⎯
4 bpp
8 bits
Not more than 8 bursts
(unpacked) 9 bits
Not more than 16
bursts
10 bits
⎯
8 bpp
8 bits
Not more than 8 bursts
9 bits
Not more than 16
bursts
10 bits
⎯
Note: * Specify the data so that the data of the number of line specified as burst length can be
stored in the same ROW address of SDRAM.
Rev. 2.00 Mar. 14, 2008 Page 1408 of 1824
REJ09B0290-0200