SH7263 Datasheet, PDF (53/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 1 Overview
Classification Symbol
I/O Name
Function
Controller area
network
(RCAN-TL1)
CTx0, CTx1
CRx0, CRx1
O CAN bus transmit Output pin for transmit data on the
data
CAN bus.
I CAN bus receive Output pin for receive data on the
data
CAN bus.
IEBus^TM
IETxD
controller (IEB) _IERxD
O IEB transmit data Output pin for transmit data on IEB.
I IEB receive data Input pin for receive data on IEB.
AND/NAND
flash memory
controller
(FLCTL)
FOE
O Flash memory Address latch enable: Asserted for
output enable address output and negated for data
I/O.
Output enable: Asserted for data
input/status read.
FSC
O Flash memory Read enable: Reads data at falling
serial clock
edge.
FCE
Serial clock: Inputs/outputs data in
synchronization with the signal.
O Flash memory Chip enable: Enables the flash
chip enable
memory connected to this LSI.
FCDE
O Flash memory Command latch enable: Asserted at
command data command output.
enable
Command data enable: Asserted at
command output.
FRB
FWE
I Flash memory Ready/busy: High level indicates
ready/busy
ready state and low level indicates
busy state.
O Flash memory Write enable: Flash memory latches
write enable
commands, addresses, and data at
rising edge.
NAF7 to NAF0 I/O Flash memory
data
Data I/O pins.
Rev. 2.00 Mar. 14, 2008 Page 19 of 1824
REJ09B0290-0200