SH7263 Datasheet, PDF (618/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1)When rewriting the buffer register within 1 carrier cycle from TGIA_3 interrupt
TGIA_3 interrupt generation
TGIA_3 interrupt generation
TCNT_3
TCNT_4
Buffer transfer-
enabled period
TITCR[6:4]
TITCNT[6:4]
Buffer register
Temporary register
General register
Buffer register rewrite timing
0
1
Data
Data
Data
Buffer register rewrite timing
2
2
0
Data1
Data1
Data1
1
Data2
Data2
Data2
(2)When rewriting the buffer register after passing 1 carrier cycle from TGIA_3 interrupt
TGIA_3 interrupt generation
TGIA_3 interrupt generation
TCNT_3
TCNT_4
Buffer transfer-
enabled period
TITCR[6:4]
Buffer register rewrite timing
TITCNT[6:4]
Buffer register
0
1
2
0
Data
1
Data1
Temporary register
Data
General register
Data
Note: * The MD bits 3 to in TMDR3, buffer transfer at the crest is selected.
The skipping count is set to two.
T3AEN and T4VEN are set to 1 and 0.
Data1
Data1
Figure 11.71 Example of Operation when Buffer Transfer is Linked with Interrupt
Skipping (BTE1 = 1 and BTE0 = 0)
Rev. 2.00 Mar. 14, 2008 Page 584 of 1824
REJ09B0290-0200