SH7263 Datasheet, PDF (1016/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
19.4.2 Configuration of RCAN-TL1
RCAN-TL1 is considered in configuration mode or after a H/W (Power On Reset)/S/W (MCR[0])
reset or when in Halt mode. In both conditions RCAN-TL1 cannot join the CAN Bus activity and
configuration changes have no impact on the traffic on the CAN Bus.
• After a Reset request
The following sequence must be implemented to configure the RCAN-TL1 after (S/W or H/W)
reset. After reset, all the registers are initialised, therefore, RCAN-TL1 needs to be configured
before joining the CAN bus activity. Please read the notes carefully.
Power On/SW Reset*¹
Reset Sequence
Configuration Mode
MCR[0] = 1 (automatically
in hardware reset only)
IRR[0] = 1, GSR[3] = 1
(automatically)
No
GSR[3] = 0?
Yes
Clear IRR[0] Bit
Configure MCR[15]
Clear Required IMR Bits
RCAN-TL1 Timer Reg Setting
Mailbox Setting
(STD-ID, EXT-ID, LAFM, DLC,
RTR, IDE, MBC, MBIMR, DART,
ATX, NMC, Tx-Trigger
Time Message-Data)*²
RCAN-TL1 is in Tx_Rx Mode
- Set TXPR to start transmission
- or stay idle to receive
Transmission_Reception
(Tx_Rx) Mode
Detect 11 recessive bits and
Join the CAN bus activity
Receive*³
Transmit*³ Timer Start*⁴
Set Bit Timing (BCR)
Clear MCR[0]
Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.
2. Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC.
3. If there is no TXPR set, RCAN-TL1 will receive the next incoming message. If there is a TXPR(s)
set, RCAN-TL1 will start transmission of the message and will be arbitrated by the CAN bus.
If it loses the arbitration, it will become a receiver.
4. Timer can be started at any time after the Timer Control regs and Tx-Trigger Time are set.
Figure 19.14 Reset Sequence
Rev. 2.00 Mar. 14, 2008 Page 982 of 1824
REJ09B0290-0200