SH7263 Datasheet, PDF (860/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Figure 17.1 shows a block diagram of the I²C bus interface 3.
Transfer clock
generation
circuit
SCL
Output
control
Noise filter
SDA
Output
control
Transmission/
reception
control circuit
ICDRT
ICDRS
ICCR1
ICCR2
ICMR
SAR
Noise canceler
ICDRR
Address
comparator
Bus state
decision circuit
NF2CYC
Arbitration
decision circuit
[Legend]
ICCR1:
ICCR2:
ICMR:
ICSR:
ICIER:
ICDRT:
ICDRR:
ICDRS:
SAR:
NF2CYC:
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus status register
I²C bus interrupt enable register
I²C bus transmit data register
I²C bus receive data register
I²C bus shift register
Slave address register
NF2CYC register
ICIER
ICSR
Interrupt
generator
Figure 17.1 Block Diagram of I²C Bus Interface 3
Interrupt
request
Rev. 2.00 Mar. 14, 2008 Page 826 of 1824
REJ09B0290-0200