SH7263 Datasheet, PDF (454/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
Transfer
DMA Transfer Request Signal Source
Transfer Bus
Destination Mode
1000
011011 01 IIC3_3
transmission
TXI3 (transmission data empty) Any
ICDRT3
Cycle
steal
10 IIC3_3
reception
RXI3 (reception data full)
ICDRR3 Any
011100 11 ROM-DEC
IREADY (decode end)
STRMDOUT Any
Cycle
steal or
burst
100000 01 SCIF_0
transmission
TXI0 (transmission FIFO data Any
empty)
SCFTDR_0 Cycle
steal
10 SCIF_0
reception
RXI0 (reception FIFO data full) SCFRDR_0 Any
100001 01 SCIF_1
transmission
TXI1 (transmit FIFO data empty) Any
SCFTDR_1
10 SCIF_1
reception
RXI1 (reception FIFO data full) SCFRDR_1 Any
100010 01 SCIF_2
transmission
TXI2 (transmission FIFO data Any
empty)
SCFTDR_2
10 SCIF_2
reception
RXI2 (reception FIFO data full) SCFRDR_2 Any
100011 01 SCIF_3
transmission
TXI3 (transmission FIFO data Any
empty)
SCFTDR_3
10 SCIF_3
reception
RXI3 (reception FIFO data full) SCFRDR_3 Any
101100 11 A/D converter ADI (A/D conversion end)
ADDR
Any
Cycle
steal
101110 11 FLCTL data part Transmission FIFO data empty
transmission
FLCTL data part Reception FIFO data full
reception
Any
FLDTFIFO Cycle
steal
FLDTFIFO Any
Rev. 2.00 Mar. 14, 2008 Page 420 of 1824
REJ09B0290-0200