SH7263 Datasheet, PDF (209/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Number of States
Item
Peripheral
Module
(Other than
NMI
User Break H-UDI
IRQ, PINT USB
USB)
Remarks
Interrupt No
response register
time
banking
Min. 5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
4 Bcyc +
m1 + m2
5 Icyc +
2 Bcyc +
m1 + m2
200-MHz operation*¹*²:
0.040 to 0.110 μs
Max. 6 Icyc +
2 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
7 Icyc +
2(m1 + m2) +
m3
6 Icyc +
1 Pcyc +
2(m1 + m2) +
m3
6 Icyc +
3 Bcyc +
1 Pcyc +
2(m1 + m2) +
m3
6 Icyc +
4 Bcyc +
2(m1 + m2) +
m3
6 Icyc +
2 Bcyc +
2(m1 + m2) +
m3
200-MHz operation*¹*²:
0.060 to 0.130 μs
Register Min. ⎯
⎯
5 Icyc +
5 Icyc +
5 Icyc +
5 Icyc +
200-MHz operation*¹*²:
banking
1 Pcyc +
3 Bcyc +
4 Bcyc +
2 Bcyc +
0.070 to 0.110 μs
without
m1 + m2
1 Pcyc +
m1 + m2
m1 + m2
register
m1 + m2
bank
Max. ⎯
⎯
14 Icyc +
14 Icyc +
14 Icyc +
14 Icyc +
200-MHz operation*¹*²:
overflow
1 Pcyc +
3 Bcyc +
4 Bcyc +
2 Bcyc +
0.120 to 0.155 μs
m1 + m2
1 Pcyc +
m1 + m2
m1 + m2
m1 + m2
Register Min. ⎯
⎯
5 Icyc +
5 Icyc +
5 Icyc +
5 Icyc +
200-MHz operation*¹*²:
banking
1 Pcyc +
3 Bcyc +
4 Bcyc +
2 Bcyc +
0.065 to 0.110 μs
with
m1 + m2
1 Pcyc +
m1 + m2
m1 + m2
register
m1 + m2
bank
Max. ⎯
⎯
5 Icyc +
5 Icyc +
5 Icyc +
5 Icyc +
200-MHz operation*¹*²:
overflow
1 Pcyc + m1 + 3 Bcyc +
4 Bcyc +
2 Bcyc +
0.160 to 0.205 μs
m2 + 19(m4) 1 Pcyc + m1 + m1 + m2 + m1 + m2 +
m2 + 19(m4) 19(m4)
19(m4)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
stack.
1. In the case that m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case that (Iφ, Bφ, Pφ) = (200 MHz, 66 MHz, 33 MHz).
Rev. 2.00 Mar. 14, 2008 Page 175 of 1824
REJ09B0290-0200