SH7263 Datasheet, PDF (1413/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
When a DSTN panel is used, LDSARL specifies the fetch start address for the lower side of the
panel.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
- SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16
Initial value: 0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SAL15 SAL14 SAL13 SAL12 SAL11 SAL10 SAL9 SAL8 SAL7 SAL6 SAL5 SAL4 -
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
Bit
Bit Name
31 to 28 ⎯
27, 26 ⎯
25 to 4 SAL25 to
SAL4
3 to 0 ⎯
Initial
Value R/W
All 0 R
All 1 R
All 0 R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
Start Address for Lower Panel Display Data Fetch
The start address for data fetch of the display data must
be set within the synchronous DRAM area of area 3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data
corresponding to the lower panel
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1379 of 1824
REJ09B0290-0200