SH7263 Datasheet, PDF (828/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
3
TEND
0
R/W
2
TDRE
1
R/W
1
RDRF
0
R/W
Description
Transmit End
[Setting conditions]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to
[Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
• When the DMAC is activated by an SSTXI interrupt
and transmit data is written to SSTDR by the DMAC
transfer
Receive Data Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
• When the DMAC is activated by an SSRXI interrupt
and receive data is read from SSRDR by the DMAC
transfer
Rev. 2.00 Mar. 14, 2008 Page 794 of 1824
REJ09B0290-0200