SH7263 Datasheet, PDF (579/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) Procedure for Selecting the Reset-Synchronized PWM Mode
Figure 11.35 shows an example of procedure for selecting the reset synchronized PWM mode.
Reset-synchronized
PWM mode
Stop counting
Select counter clock and
counter clear source
[1] Clear the CST3 and CST4 bits in the TSTR
to 0 to halt the counting of TCNT. The
reset-synchronized PWM mode must be set
up while TCNT_3 and TCNT_4 are halted.
[1]
[2] Set bits TPSC2-TPSC0 and CKEG1 and
CKEG0 in the TCR_3 to select the counter
clock and clock edge for channel 3. Set bits
[2]
CCLR2-CCLR0 in the TCR_3 to select TGRA
compare-match as a counter clear source.
Brushless DC motor
control setting
Set TCNT
[3] When performing brushless DC motor control,
[3]
set bit BDC in the timer gate control register
(TGCR) and set the feedback signal input source
and output chopping or gate signal direct output.
[4]
[4] Reset TCNT_3 and TCNT_4 to H'0000.
Set TGR
[5]
PWM cycle output enabling,
PWM output level setting ^[6]
[5] TGRA_3 is the period register. Set the waveform
period value in TGRA_3. Set the transition timing
of the PWM output waveforms in TGRB_3,
TGRA_4, and TGRB_4. Set times within the
compare-match range of TCNT_3.
X ≤ TGRA_3 (X: set value).
Set reset-synchronized
PWM mode
Enable waveform output
[7]
[6] Select enabling/disabling of toggle output
synchronized with the PMW cycle using bit PSYE
in the timer output control register (TOCR), and set
the PWM output level with bits OLSP and OLSN.
[8]
When specifying the PWM output level by using TOLBR
as a buffer for TOCR_2, see figure 10.3.
PFC setting
[9] [7] Set bits MD3-MD0 in TMDR_3 to B'1000 to select
the reset-synchronized PWM mode. Do not set to TMDR_4.
Start count operation
[10] [8] Set the enabling/disabling of the PWM waveform output
pin in TOER.
Reset-synchronized PWM mode
[9] Set the port control register and the port I/O register.
[10] Set the CST3 bit in the TSTR to 1 to start the count
operation.
Note: The output waveform starts to toggle operation at the point of
TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty.
Figure 11.35 Procedure for Selecting Reset-Synchronized PWM Mode
Rev. 2.00 Mar. 14, 2008 Page 545 of 1824
REJ09B0290-0200