SH7263 Datasheet, PDF (1375/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
(3) DMA Transfers (D0FIFO/D1FIFO port)
(a) Overview of DMA Transfers
For pipes 1 to 7, the FIFO port can be accessed using the DMAC. When accessing the buffer for
the pipe targeted for DMA transfer is enabled, a DMA transfer request is issued.
The unit of transfer to the FIFO port should be selected using the MBW bit in DnFIFOSEL and
the pipe targeted for the DMA transfer should be selected using the CURPIPE bit. The selected
pipe should not be changed during the DMA transfer.
(b) Auto Recognition of DMA Transfer Completion
With this module, it is possible to complete FIFO data writing through DMA transfer by
controlling DMA transfer end signal input. A DMA transfer signal is output from the DMAC
when the number of DMA transfers specified in the DMA transfer count register (DMATCR) has
been performed. When a DMA transfer end signal is sampled, the module enables buffer memory
transmission (the same condition as when BVAL = 1). The TENDE bit in DnFBCFG can be used
to specify whether a DMA transfer end signal is sampled or not.
(c) Zero-Length Packet Addition Mode (D0FIFO/D1FIFO Port Writing Direction)
With this module, it is possible to add and send one zero-length packet after all of the data has
been sent, under the condition below, by setting 1 to the DEZPM bit in DnFIFOSEL. This
function can be set only if the buffer memory writing direction has been set (a pipe in the sending
direction has been set for the CURPIPE bits).
• If the number of data bytes written to the buffer memory is a multiple of the integer for the
maximum packet size when a DMA transfer end signal is sampled.
(d) DnFIFO Auto Clear Mode (D0FIFO/D1FIFO Port Reading Direction)
If 1 is set for the DCLRM bit in DnFIFOSEL, the module automatically clears the buffer memory
of the corresponding pipe when reading of the data from the buffer memory has been completed.
Table 25.21 shows the packet reception and buffer memory clearing processing for each of the
various settings. As shown, the buffer clear conditions depend on the value set to the BFRE bit.
Using the DCLRM bit eliminates the need for the buffer to be cleared by software even if a
situation occurs that necessitates clearing of the buffer. This makes it possible to carry out DMA
transfers without involving software.
This function can be set only in the buffer memory reading direction.
Rev. 2.00 Mar. 14, 2008 Page 1341 of 1824
REJ09B0290-0200