SH7263 Datasheet, PDF (1473/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
Bit
9
8
7 to 2
1, 0
Initial
Bit Name Value R/W Description
OED
0
R/W Output Data Endian
Specifies the endian format of the output data.
0: Big endian
1: Little endian
OEN
0
R/W Output Data FIFO Full Interrupt Enable
Enables/disables the output data FIFO full interrupt
request to be issued when the number of data units in
the output FIFO becomes equal to or greater than the
number specified by the OFTRG1 and OFTRG0 bits,
thus resulting in the OINT bit in SRC status register
(SRCSTAT) being set to 1.
0: Output data FIFO full interrupt is disabled.
1: Output data FIFO full interrupt is enabled.
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
OFTRG[1:0] 00
R/W Output FIFO Data Trigger Number
Specifies the condition in terms of the number on
which the OINT bit in the SRC status register
(SRCSTAT) is set to 1. When the number of data
units in the output FIFO becomes equal to or greater
than the number listed below, the OINT bit is set to 1.
00: 1
01: 2
10: 4
11: 6
Rev. 2.00 Mar. 14, 2008 Page 1439 of 1824
REJ09B0290-0200