SH7263 Datasheet, PDF (1421/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VSYNW VSYNW VSYNW VSYNW
3
2
1
0
-
VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP VSYNP
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
R/W: R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
VSYNW3 0
R/W Vertical Sync Signal Width
14
VSYNW2 0
R/W Set the width of the vertical sync signals (FLM and
13
VSYNW1 0
R/W ^{Vsync) (unit: line).}
12
VSYNW0 0
R/W ^{Specify to the value of (the vertical sync signal width) -1.}
Example: For a vertical sync signal width of 1 line.
VSYNW = (1-1) = 0 = H'0
11
⎯
0
R Reserved
This bit is always read as 0. The write value should
always be 0.
10
VSYNP10 0
R/W Vertical Sync Signal Output Position
9
VSYNP9 0
R/W Set the output position of the vertical sync signals (FLM
8
VSYNP8 1
R/W ^{and Vsync) (unit: line).}
7
VSYNP7 1
R/W ^{Specify to the value of (the number of vertical sync signal}
output position) -2.
6
VSYNP6 1
R/W
DSTN should be set to an odd number value. It is
5
VSYNP5 0
R/W _{handled as (setting value+1)/2.}
4
VSYNP4 1
R/W _{Example: For an 480-line LCD module and a vertical}
3
VSYNP3 1
R/W ^{retrace period of 0 lines (in other words, VTLN=479 and}
2
VSYNP2 1
R/W ^{the vertical sync signal is active for the first line):}
1
VSYNP1 1
R/W ^{• Single display}
0
VSYNP0 1
R/W
VSYNP = [(1-1)+VTLN]mod(VTLN+1)
= [(1-1)+479]mod(479+1)
= 479mod480 = 479 =H'1DF
• Dual displays
VSYNP = [(1-1)×2+VTLN]mod(VTLN+1)
= [(1-1)×2+479]mod(479+1)
= 479mod480 = 479 =H'1DF
Rev. 2.00 Mar. 14, 2008 Page 1387 of 1824
REJ09B0290-0200