SH7263 Datasheet, PDF (1163/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.50 Interrupt Source Mask Control Register (INHINT)
The interrupt source mask control register (INHINT) controls masking of various interrupt
requests in the CD-ROM decoder.
Bit:
Initial value:
R/W:
7
INH
ISEC
0
R/W
6
INH
ITARG
0
R/W
5
INH
ISY
0
R/W
4
INH
IERR
0
R/W
3
2
1
0
INH INH PREINH PREINH
IBUF IREADY REQDM IREADY
0
0
0
0
R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
7
INHISEC
0
R/W ISEC Interrupt Mask
When set to 1, inhibits ISEC interrupt requests
6
INHITARG 0
R/W ITARG Interrupt Mask
When set to 1, inhibits ITARG interrupt requests
5
INHISY
0
R/W ISY Interrupt Mask
When set to 1, inhibits ISY interrupt requests
4
INHIERR
0
R/W IERR Interrupt Mask
When set to 1, inhibits IERR interrupt requests
3
INHIBUF
0
R/W IBUF Interrupt Mask
When set to 1, inhibits IBUF interrupt requests
2
INHIREADY 0
R/W IREADY Interrupt Mask
When set to 1, inhibits IREADY interrupt requests
1
PREINH
0
REQDM
R/W Inhibits setting of the DMA-transfer-request interrupt
source flag for the output data stream.
When this bit is set to 1, the DMA-transfer-request
interrupt source is not retained.
0
PREINH
0
IREADY
R/W Inhibits setting of the IREADY interrupt flag.
When this bit is set to 1, the IREADY interrupt source
not retained.
Rev. 2.00 Mar. 14, 2008 Page 1129 of 1824
REJ09B0290-0200