SH7263 Datasheet, PDF (118/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.5 Processing States
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Manual reset from any state
Power-on reset from any state
Manual reset state
Power-on reset state
Reset canceled
Reset state
Interrupt source or
DMA address error occurs
Exception
handling state
Bus request
cleared
Exception
handling
Bus request _source
generated _occurs
Bus-released state
Bus request
cleared
Exception
handling
ends
NMI interrupt or
IRQ interrupt occurs
NMI interrupt,
IRQ interrupt*,
manual reset,
and power-on
reset
Bus request
generated
Bus request
generated
Bus request
cleared
Program execution state
STBY bit cleared
for SLEEP
instruction
STBY bit set
and DEEP bit
cleared for SLEEP
instruction
STBY and DEEP bits set
for SLEEP
instruction
Sleep mode
Software standby mode
Note: * IRQ can be released only by PE11 to PE4.
Deep standby mode
Power-down state
Figure 2.6 Transitions between Processing States
Rev. 2.00 Mar. 14, 2008 Page 84 of 1824
REJ09B0290-0200