SH7263 Datasheet, PDF (1469/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
27.2 Register Descriptions
The SRC has the registers listed in table 27.1.
Table 27.1 Register Configuration
Register Name
Abbreviation R/W Initial Value Address Access Size
SRC input data register
SRCID
R/W H'00000000 H'FFFF4000 16, 32
SRC output data register SRCOD
R
H'00000000 H'FFFF4004 16, 32
SRC input data control
register
SRCIDCTRL R/W H'0000
H'FFFF4008 16
SRC output data control
register
SRCODCTRL R/W H'0000
H'FFFF400A 16
SRC control register
SRCCTRL
R/W H'0000
H'FFFF400C 16
SRC status register
SRCSTAT
R/(W)* H'0002
H'FFFF400E 16
Note: * Bits 15 to 3 are read-only. Only 0 can be written to bits 2 to 0 after having read as 1.
27.2.1 SRC Input Data Register (SRCID)
SRCID is a 32-bit readable/writable register that is used to input the data before sampling rate
conversion. All the bits are read as 0. The data input to SRCID is stored in the 16-stage input data
FIFO. When the number of data units in the input data FIFO is 16, writing to SRCID has no effect.
For stereo data, bits 31 to 16 are for ch 0 data, and bits 15 to 0 are for ch 1 data. For monaural
data, data in bits 31 to 16 is valid, and data in bits 15 to 0 is invalid.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The data subject to sampling rate conversion is aligned differently depending on the IED bit
setting in SRCIDCTRL. Table 27.2 shows the relationship between the IED bit setting and data
alignment.
Rev. 2.00 Mar. 14, 2008 Page 1435 of 1824
REJ09B0290-0200