SH7263 Datasheet, PDF (217/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.8.3 Save and Restore Operations after Saving to All Banks
If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the
CPU in a state where saving has been performed to all register banks, automatic saving to the
stack is performed instead of register bank saving if the BOVE bit in the bank number register
(IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception
occurs and data is not saved to the stack.
Save and restore operations when using the stack are as follows:
(1) Saving to Stack
1. The status register (SR) and program counter (PC) are saved to the stack during interrupt
exception handling.
2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to
the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14,
R13, …, R1, and R0.
3. The register bank overflow bit (BO) in SR is set to 1.
4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
maximum value of 15.
(2) Restoration from Stack
When the RESBANK (restore from register bank) instruction is executed with the register bank
overflow bit (BO) in SR set to 1, the CPU operates as follows:
1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored
from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14,
PR, GBR, MACH, and MACL.
2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
maximum value of 15.
Rev. 2.00 Mar. 14, 2008 Page 183 of 1824
REJ09B0290-0200