SH7263 Datasheet, PDF (1021/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
19.4.3 Message Transmission Sequence
• Message Transmission Request
The following sequence is an example to transmit a CAN frame onto the bus. As described in the
previous register section, please note that IRR8 is set when one of the TXACK or ABACK bits is
set, meaning one of the Mailboxes has completed its transmission or transmission abortion and is
now ready to be updated for the next transmission, whereas, the GSR2 means that there is
currently no transmission request made (No TXPR flags set).
RCAN-TL1 is in Tx_Rx Mode
(MBC[x] = 0)
Mailbox[x] is ready
to be updated for
next transmission
Update Message Data of
Mailbox[x]
Clear TXACK[x]
Write '1' to the TXPR[x] bit
at any desired time
Yes
TXACK[x] set?
No
Waiting for
Interrupt
Internal Arbitration
No
'x' Highest Priority?
Yes
Yes
IRR8 set?
No
Waiting for
Interrupt
Transmission Start
CAN Bus
Arbitration
End Of Frame
CAN Bus
Figure 19.16 Transmission request
• Internal Arbitration for transmission
The following diagram explains how RCAN-TL1 manages to schedule transmission-requested
messages in the correct order based on the CAN identifier. ‘Internal arbitration’ picks up the
highest priority message amongst transmit-requested messages.
Rev. 2.00 Mar. 14, 2008 Page 987 of 1824
REJ09B0290-0200