SH7263 Datasheet, PDF (269/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Name
WE1/DQMLU/WE
WE0/DQMLL
RASU, RASL
CASU, CASL
CKE
FRAME
WAIT
BREQ
BACK
REFOUT
IOIS16
MD
I/O
Function
Output Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a SRAM with byte
selection is connected.
Functions as the select signals for D15 to D8 when SDRAM is
connected.
Functions as a strobe signal for indicating memory write cycles when
PCMCIA is used.
Output Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a SRAM with byte
selection is connected.
Functions as the select signals for D7 to D0 when SDRAM is
connected.
Output Connects to RAS pin when SDRAM is connected.
Output Connects to CAS pin when SDRAM is connected.
Output Connects to CKE pin when SDRAM is connected.
Output Functions as FRAME signal when connected to burst MPX-I/O
interface
Input External wait input
Input Bus request input
Output Bus enable output
Output Refresh request output in bus-released state
Input Indicates 16-bit I/O of PCMIA.
Enabled only in little endian mode. The pin should be driven low in
big endian mode.
Input Selects bus width of area 0 and initial bus width of areas 1 to 7.
Rev. 2.00 Mar. 14, 2008 Page 235 of 1824
REJ09B0290-0200