SH7263 Datasheet, PDF (175/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
Section 6 Interrupt Controller (INTC)
The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the
user to process interrupt requests according to the user-set priority.
6.1 Features
• 16 levels of interrupt priority can be set
By setting the fifteen interrupt priority registers, the priorities of IRQ interrupts, PINT
interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request
sources.
• NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as the noise
canceler function.
• Occurrence of interrupt can be reported externally (IRQOUT pin)
For example, when this LSI has released the bus mastership, this LSI can inform the external
bus master of occurrence of an on-chip peripheral module interrupt and request for the bus
mastership.
• Register banks
This LSI has register banks that enable register saving and restoration required in the interrupt
processing to be performed at high speed.
Rev. 2.00 Mar. 14, 2008 Page 141 of 1824
REJ09B0290-0200