SH7263 Datasheet, PDF (1344/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Access Transfer
Direction Direction Pipe
Read
Receive 1 to 7
Write
Transmit DCP
1 to 7
Conditions under which BRDY Interrupt is
BFRE DBLB Generated
1
Don't (1), (2) or (3) below:
care _{(1) Zero-length packet reception}
(2) After a short packet reception, reading data
of the packet is complete.
(3) After the transaction counter ends, reading
data of the last packet is complete.
⎯
⎯
Not generated
0
0
(1), (2), (3) or (4) below:
(1) Software changes the direction of transfer
from receiving to transmitting.
(2) Transmission of data to the host is
completed when there are data waiting to be
transmitted.
(3) Software sets the ACLRM bit in PIPEnCTR
to 1 when there are data waiting to be
transmitted.
(4) Software sets the SCLR bit in CFIFOSIE to
1 when there are data waiting to be
transmitted.
Rev. 2.00 Mar. 14, 2008 Page 1310 of 1824
REJ09B0290-0200