SH7263 Datasheet, PDF (1307/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1
PIPE1BRDY 0
R/W*¹ BRDY Interrupt Status for PIPE1*²
0: Interrupts not generated
1: Interrupts generated
0
PIPE0BRDY 0
R/W*¹ BRDY Interrupt Status for PIPE0*²
0: Interrupts not generated
1: Interrupts generated
Notes: 1. Only 0 can be written to.
2. If multiple sources have occurred, an access cycle of at least 140 ns and 3 bus clock
cycles is required in order to clear the bits in succession, not simultaneously.
Rev. 2.00 Mar. 14, 2008 Page 1273 of 1824
REJ09B0290-0200