SH7263 Datasheet, PDF (1594/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
6
MSTP46 1
R/W Module Stop 46
When the MSTP46 bit is set to 1, the supply of the
clock to the SCIF1 is halted.
0: SCIF1 runs.
1: Clock supply to SCIF1 is halted.
5
MSTP45 1
R/W Module Stop 45
When the MSTP45 bit is set to 1, the supply of the
clock to the SCIF2 is halted.
0: SCIF2 runs.
1: Clock supply to SCIF2 is halted.
4
MSTP44 1
R/W Module Stop 44
When the MSTP44 bit is set to 1, the supply of the
clock to the SCIF3 is halted.
0: SCIF3 runs.
1: Clock supply to SCIF3 is halted.
3
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
2
MSTP42 1
R/W Module Stop 42
When the MSTP42 bit is set to 1, the supply of the
clock to the CMT is halted.
0: CMT runs.
1: Clock supply to CMT is halted.
1
MSTP41 1
R/W Module Stop 41
When the MSTP41 bit is set to 1, the supply of the
clock to the LCDC is halted.
0: LCDC runs.
1: Clock supply to LCDC is halted.
0
MSTP40 1
R/W Module Stop 40
When the MSTP40 bit is set to 1, the supply of the
clock to the FLCTL is halted.
0: FLCTL runs.
1: Clock supply to FLCTL is halted.
Rev. 2.00 Mar. 14, 2008 Page 1560 of 1824
REJ09B0290-0200