SH7263 Datasheet, PDF (781/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
10 to 8
7, 6
Bit Name
Initial
Value R/W
RSTRG[2:0] 000 R/W
RTRG[1:0] 00
R/W
Description
RTS Output Active Trigger
When the quantity of receive data in receive FIFO data
register (SCFRDR) becomes more than the number
shown below, RTS signal is set to high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Receive FIFO Data Trigger
• Set the quantity of receive data which sets the receive
data full (RDF) flag in the serial status register
(SCFSR). The RDF flag is set to 1 when the quantity
of receive data stored in the receive FIFO register
(SCFRDR) is increased more than the set trigger
number shown below.
• Asynchronous mode • Clock synchronous mode
00: 1
00: 1
01: 4
01: 2
10: 8
10: 8
11: 14
11: 14
Note:
In clock synchronous mode, to transfer the
receive data using DMAC, set the receive trigger
number to 1. If set to other than 1, CPU must
read the receive data left in SCFRDR.
Rev. 2.00 Mar. 14, 2008 Page 747 of 1824
REJ09B0290-0200