SH7263 Datasheet, PDF (1219/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Section 24 AND/NAND Flash Memory Controller
(FLCTL)
The AND/NAND flash memory controller (FLCTL) provides interfaces for an external AND-type
flash memory and NAND-type flash memory. To take measures for errors specific to flash
memory, the ECC-code generation function and error detection function are available.
Note: The flash memory using Multi Level Cell (MLC) technology is not supported by this LSI.
24.1 Features
(1) AND-Type Flash Memory Interface
• Interface directly connectable to AND-type flash memory
• Read or write in sector units (512 + 16 bytes) and ECC processing executed
An access unit of 2048 + 64 bytes, referred to as a page, is used in some datasheets for AND-
type flash memory. In this manual, an access unit of 512 + 16 bytes, referred to as a sector, is
always used. For products in which 2048 + 64 bytes is referred to as a page, a page is divided
into units of 512 + 16 bytes (i.e. four sectors per page) for processing.
• Read or write in byte units
• Supports addresses for 2 Gbits and more by extension to 5-byte addresses
(2) NAND-Type Flash Memory Interface
• Interface directly connectable to NAND-type flash memory
• Read or write in sector units (512 + 16 bytes) and ECC processing executed
An access unit of 2048 + 64 bytes, referred to as a page, is used in some datasheets for NAND-
type flash memory. In this manual, an access unit of 512 + 16 bytes, referred to as a sector, is
always used. For products in which 2048 + 64 bytes is referred to as a page, a page is divided
into units of 512 + 16 bytes (i.e. four sectors per page) for processing.
• Read or write in byte units
• Supports addresses for 2 Gbits and more by extension to 5-byte addresses
Rev. 2.00 Mar. 14, 2008 Page 1185 of 1824
REJ09B0290-0200