SH7263 Datasheet, PDF (1289/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.9 FIFO Port SIE Register (CFIFOSIE)
CFIFOSIE is a register that controls the SIE functions of the CFIFO port. This register switches
the access right between the SIE and CPU, clears the SIE buffer memory, and checks whether the
SIE buffer is busy or not. This register is not operational when DCP is selected.
This register is initialized by a power-on reset and a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TGL SCLR SBUSY -
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15
TGL
0
R/W* Access Right Switch
Sets the buffer memory on the SIE side to the CPU
side. Set the PID bits to NAK and check that the SIE
does not access the buffer memory with the SBUSY
bit (that the SBUSY bit is cleared to 0). Then write
the TGL bit (toggle operation). This bit is valid only
for pipes for which the receiving direction (reading
from the buffer memory) has been set.
0: Invalid
1: Switches the access right
14
SCLR
0
R/W SIE Buffer Clear
Clears the buffer memory on the SIE side. Set the
PID bits to NAK and check that the SIE does not
access the buffer (SBUSY = 0). Then clear the
buffer. This bit is valid only for pipes for which the
transmitting direction (writing to the buffer memory)
has been set.
0: Invalid
1: Clears buffer memory on SIE side
Rev. 2.00 Mar. 14, 2008 Page 1255 of 1824
REJ09B0290-0200