SH7263 Datasheet, PDF (15/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

11.3.2 Timer Mode Register (TMDR) ............................................................................. 455
11.3.3 Timer I/O Control Register (TIOR) ...................................................................... 458
11.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 476
11.3.5 Timer Status Register (TSR)................................................................................. 479
11.3.6 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 484
11.3.7 Timer Input Capture Control Register (TICCR) ................................................... 485
11.3.8 Timer A/D Converter Start Request Control Register (TADCR) ......................... 486
11.3.9 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 489
11.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 489
11.3.11 Timer Counter (TCNT)......................................................................................... 490
11.3.12 Timer General Register (TGR) ............................................................................. 490
11.3.13 Timer Start Register (TSTR) ................................................................................ 491
11.3.14 Timer Synchronous Register (TSYR)................................................................... 492
11.3.15 Timer Read/Write Enable Register (TRWER) ..................................................... 494
11.3.16 Timer Output Master Enable Register (TOER) .................................................... 495
11.3.17 Timer Output Control Register 1 (TOCR1) .......................................................... 496
11.3.18 Timer Output Control Register 2 (TOCR2) .......................................................... 499
11.3.19 Timer Output Level Buffer Register (TOLBR) .................................................... 502
11.3.20 Timer Gate Control Register (TGCR) .................................................................. 503
11.3.21 Timer Subcounter (TCNTS) ................................................................................. 505
11.3.22 Timer Dead Time Data Register (TDDR)............................................................. 506
11.3.23 Timer Cycle Data Register (TCDR) ..................................................................... 506
11.3.24 Timer Cycle Buffer Register (TCBR)................................................................... 507
11.3.25 Timer Interrupt Skipping Set Register (TITCR) ................................................... 507
11.3.26 Timer Interrupt Skipping Counter (TITCNT)....................................................... 509
11.3.27 Timer Buffer Transfer Set Register (TBTER) ...................................................... 510
11.3.28 Timer Dead Time Enable Register (TDER).......................................................... 512
11.3.29 Timer Waveform Control Register (TWCR) ........................................................ 513
11.3.30 Bus Master Interface............................................................................................. 514
11.4 Operation ........................................................................................................................... 515
11.4.1 Basic Functions..................................................................................................... 515
11.4.2 Synchronous Operation......................................................................................... 521
11.4.3 Buffer Operation ................................................................................................... 523
11.4.4 Cascaded Operation .............................................................................................. 527
11.4.5 PWM Modes ......................................................................................................... 532
11.4.6 Phase Counting Mode........................................................................................... 537
11.4.7 Reset-Synchronized PWM Mode.......................................................................... 544
11.4.8 Complementary PWM Mode................................................................................ 547
Rev. 2.00 Mar. 14, 2008 Page xv of xxxiv
REJ09B0290-0200