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| SH7263 Datasheet, PDF (749/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series | |||
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Section 15 Serial Communication Interface with FIFO (SCIF)
Figure 15.1 shows a block diagram of the SCIF.
Module data bus
RxD
TxD
SCK
SCFRDR (16 stages) SCFTDR (16 stages)
SCSMR
SCBRR
SCLSR
SCFDR
SCEMR
SCRSR
SCTSR
SCFCR
SCFSR
Baud rate
generator
SCSCR
SCSPTR
Transmission/reception
control
Parity generation
Clock
Parity check
External clock
CTS
RTS
SCIF
[Legend]
SCRSR: Receive shift register
SCFRDR: Receive FIFO data register
SCTSR: Transmit shift register
SCFTDR: Transmit FIFO data register
SCSMR: Serial mode register
SCSCR: Serial control register
SCEMR: Serial extension mode register
SCFSR: Serial status register
SCBRR: Bit rate register
SCSPTR:Serial port register
SCFCR: FIFO control register
SCFDR: FIFO data count set register
SCLSR: Line status register
Figure 15.1 Block Diagram of SCIF
Peripheral
bus
PÏ
PÏ/4
PÏ/16
PÏ/64
TXI
RXI
ERI
BRI
Rev. 2.00 Mar. 14, 2008 Page 715 of 1824
REJ09B0290-0200
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