SH7263 Datasheet, PDF (1444/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.4.4 Data Format
1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
MSB
LSB
7 6 5 4 3 2 1 0 [Bit]
P00 P01 P02 P03 P04 P05 P06 P07 (Byte0)
P08
(Byte1)
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
+03
…
…
Display
+LAO+00 P10 P11 P12 P13 P14 P15 P16 P17
+LAO+01 P18
+LAO+02
…
Pn: Put 1-bit data
+LAO+03
…
Display Memory
LAO: Line Address Offset
—Unused bits should be 0
2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
MSB
76
P00
P04
54
P01
P05
32
P02
P06
LSB
1 0 [Bit]
P03 (Byte0)
P07 (Byte1)
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
+03
…
…
Display
+LAO+00 P10 P11 P12 P13
+LAO+01 P14 P15 P16 P17
+LAO+02
…
Pn=Pn[1:0]: Put 2-bit data
+LAO+03
…
Display Memory
LAO: Line Address Offset
—Unused bits should be 0
3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
MSB
LSB
7 6 5 4 3 2 1 0 [Bit]
P00
P01
(Byte0)
P02
P03
(Byte1)
P04
P05
(Byte2)
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
+03
…
…
Display
+LAO+00
P10
P11
Pn=Pn[3:0]: Put 4-bit data
+LAO+01
+LAO+02
+LAO+03
…
P12
P13
P14
P15
…
Display Memory
LAO: Line Address Offset
—Unused bits should be 0
4. Packed 1bpp (Pixel Alignment in Byte is Little Endian)
MSB
LSB
Address
7 6 5 4 3 2 1 0 [Bit]
+00
P07 P06 P05 P04 P03 P02 P01 P00 (Byte0)
+01
P08 (Byte1)
+02
+03
…
…
+LAO+00 P17 P16 P15 P14 P13 P12 P11 P10
+LAO+01
P18
+LAO+02
…
+LAO+03
…
Display Memory
↓ Top Left Pixel
P00 P01 P02 P03 P04 P05 P06 P07 ^…
P10 P11 P12 P13 P14 P15 P16 P17 ^…
…
…
Display
Pn: Put 1-bit data
LAO: Line Address Offset
—Unused bits should be 0
Rev. 2.00 Mar. 14, 2008 Page 1410 of 1824
REJ09B0290-0200