SH7263 Datasheet, PDF (1841/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
32.3.4 Deep Standby
Mode
(1) Transition to Deep
Standby Mode
Page
1583
(2) Canceling Deep
Standby Mode
1586
(4) Notes on Transition 1588
to Deep Standby Mode
32.4.1 Notes on Writing 1589
to Registers
32.4.2 Notice about
Deep Standby Control
Register 2 (DSCTR2)
32.4.3 Notice about
Power-On Reset
Exception Handling
1590
Revision (See Manual for Details)
Description amended
3. To cancel deep standby mode by an interrupt, set to 1 the
bit in DSSSR corresponding to the pin to be used for
cancellation. In this case, also set the input signal detection
mode (using interrupt control registers 0 and 1 (ICR0 and
ICR1) of the interrupt controller (INTC)) for the pin used for
cancellation. In the case of deep standby mode, only rising-
or falling-edge detection is valid. (Low-level detection or
both-edge detection of the IRQ signal cannot be used to
cancel deep standby mode.)
Description amended
• Canceling by an interrupt
… When deep standby mode is canceled by the falling edge of
the NMI pin, the NMI pin should be high when the CPU enters
deep standby mode (when the clock pulse stops) and should
be low when deep standby mode is canceled (when the clock
is initiated after oscillation settling). When deep standby mode
is canceled by the rising edge of the NMI pin, the NMI pin
should be low when the CPU enters deep standby mode (when
the clock pulse stops) and should be high when deep standby
mode is canceled (when the clock is initiated after oscillation
settling). (The same applies to the IRQ pin.)
Description amended
After deep standby mode is specified, interrupts other than
those set as cancel sources in the deep standby cancel source
select register are masked. If multiple interrupts are set as
cancel sources in the deep standby cancel source select
register and more than one of these cancel sources are input,
multiple cancel source flags are set.
In addition, if a SLEEP instruction to initiate the transition to
deep standby mode coincides with an NMI or IRQ interrupt, or
with a manual reset, acceptance of the interrupt may cause
cancellation of deep standby mode.
Title added
Newly added
Rev. 2.00 Mar. 14, 2008 Page 1807 of 1824
REJ09B0290-0200