SH7263 Datasheet, PDF (1353/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Setup
token reception
CTSQ = 000
setup stage
Setup token reception
CTSQ = 110
control transfer
sequence error
5
Error
detection
Setup token reception
Error detection and IN token reception
are valid at all stages in the box.
ACK
trans-
mission
CTSQ = 001
1 control read
data stage
OUT token
2
CTSQ = 010
control read
status stage
ACK
trans-
mission
4
CTSQ = 000
idle stage
4
ACK
transmission
1
CTSQ = 011
control write
data stage
IN token
3
CTSQ = 100
control write
status stage
ACK
reception
ACK
transmission
Note:
CTRT interrupts
(1) Setup stage completed
(2) Control read transfer status stage transition
(3) Control write transfer status stage transition
(4) Control transfer completed
(5) Control transfer sequence error
CTSQ = 101
1
control write
no data
status stage
ACK
reception
Figure 25.7 Control Transfer Stage Transitions
(6) Frame Update Interrupt
Figure 25.8 shows an example of the SOFR interrupt output timing of this module. When the
frame number is updated or a damaged SOF packet is detected, the SOFR interrupt is generated.
The interrupt operation should be specified using the SOFRM bit in FRMNUM.
When the host controller function is selected, SOFRM = 1 should not be set.
1. When SOFRM = 0 is set
The SOFR interrupt is generated when the frame number is updated (intervals of
approximately 1 ms). Interrupts are generated by the internal interpolation function even if an
SOF packet is damaged or missing. During high-speed communication, interrupts are
generated at the timing at which the frame number is updated (intervals of approximately 1
ms).
Rev. 2.00 Mar. 14, 2008 Page 1319 of 1824
REJ09B0290-0200