SH7263 Datasheet, PDF (1749/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
CKIO
Tr
Tc1
Trwl
A25 to A0
A12/A11^*1
t_AD1
t_AD1
t_AD1
Row
address
Column
address
t_AD1
t_AD1
t_AD1
WRITA
command
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
BS
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_DQMD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_BSD
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 35.26 Synchronous DRAM Single Write Bus Cycle
(Auto Precharge, TRWL = 1 Cycle)
Rev. 2.00 Mar. 14, 2008 Page 1715 of 1824
REJ09B0290-0200