SH7263 Datasheet, PDF (1773/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.9 SSU Timing
Table 35.14 SSU Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Item
Clock cycle
Master
Slave
Clock high pulse width
Master
Slave
Clock low pulse width
Master
Slave
Clock rise time
Clock fall time
Data input setup time
Master
Slave
Data input hold time
Master
SCS setup time
Slave
Master
SCS hold time
Slave
Master
Slave
Data output delay time
Master
Slave
Data output hold time
Master
Slave
Continuous transmission delay time Master
Slave
Slave access time
Slave out release time
Symbol Min.
tSUcyc
4
4
tHI
48
48
tLO
48
48
tRISE
⎯
tFALL
⎯
tSU
30
20
tH
0
20
tLEAD
1.5
1.5
tLAG
1.5
1.5
tOD
⎯
⎯
tOH
0
0
tTD
1.5
1.5
tSA
⎯
tREL
⎯
Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Max.
256
256
⎯
⎯
⎯
⎯
12
12
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
50
50
⎯
⎯
⎯
⎯
1
1
Unit
tpcyc
ns
ns
Figure
Figures
35.53,
35.54,
35.55,
35.56
ns
ns
ns
ns
tpcyc
tpcyc
ns
ns
tpcyc
tpcyc
Figures
tpcyc
35.55,
35.56
Rev. 2.00 Mar. 14, 2008 Page 1739 of 1824
REJ09B0290-0200