SH7263 Datasheet, PDF (1322/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.30 DCP Control Register (DCPCTR)
DCPCTR is a register that is used to confirm the buffer memory status, change and confirm the
data PID sequence bit, and set the response PID for the DCP.
This register is initialized by a power-on reset or a software reset. The CCPL and PID[2:0] bits are
initialized by a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSTS SUREQ -
-
-
-
- SQCLR SQSET SQMON -
-
- CCPL
PID[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
R/W: R R/W*² R
R
R
R
R R*¹/ R*¹/ R
R
R
R R/W R/W R/W
W*² W*²
Bit
Bit Name
15
BSTS
14
SUREQ
13 to 9 ⎯
8
SQCLR
7
SQSET
Initial
Value
0
0
All 0
0
0
R/W Description
R
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled
R/W*²
The direction of buffer access, writing or reading,
depends on the ISEL bit in CFIFOSEL.
SETUP Token Transmission
Transmits the setup packet by setting this bit to 1.
This module clears this bit when the setup
transaction is completed. While this bit is 1,
USBREQ, USBVAL, USBINDX and USBLENG
should not be written to.
0: Invalid
1: Transmits the setup packet
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R*¹/W*² Toggle Bit Clear*³*⁴
0: Invalid
1: Specifies DATA0
R*¹/W*² Toggle Bit Set*³*⁴
0: Invalid
1: Specifies DATA1
Rev. 2.00 Mar. 14, 2008 Page 1288 of 1824
REJ09B0290-0200