SH7263 Datasheet, PDF (846/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
(4) Data Transmission/Reception
Figure 16.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1. When the RDRF bit is set to 1, at the 8th rising edge of the transfer clock the
ORER bit in SSSR is set to 1, an overrun error (SSERI) is generated, and both transmission and
reception are stopped. Transmission and reception are not possible while the ORER bit is set to 1.
To resume transmission and reception, clear the ORER bit to 0.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
Rev. 2.00 Mar. 14, 2008 Page 812 of 1824
REJ09B0290-0200