SH7263 Datasheet, PDF (400/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
9.5.10 Burst MPX-I/O Interface
Figure 9.47 shows an example of a connection between the LSI and the burst MPX device.
Figures 9.48 to 9.51 show the burst MPX space access timings.
Area 6 can be specified as the address/data multiplex I/O (MPX-I/O) interface using the TYPE2 to
TYPE0 bits in CS6BCR. This MPX-I/O interface enables the LSI to be easily connected to an
external memory controller chip that uses an address/data multiplexed 32-bit single bus. In this
case, the address and the access size for the MPX-I/O interface are output to D25 to D0 and D31
to D29, respectively, in address cycles. For the access sizes of D31 to D29, see the description of
CS6WCR for the burst MPX-I/O in section 9.4.3 (5), Burst MPX-I/O.
Address pins A25 to A0 are used to output normal addresses.
In the burst MPX-I/O interface, the bus size is fixed at 32 bits. The BSZ1 and BSZ0 bits in
CS6BCR must be specified as 32 bits. In the burst MPX-I/O interface, a software wait and
hardware wait using the WAIT pin can be inserted.
In read cycles, a wait cycle is inserted automatically following the address output even if the
software wait insertion is specified as 0.
This LSI
CS6
BS
FRAME
RD/WR
D31
D0
WAIT
64K × 16-bit
SRAM
CS
BS
FRAME
WE
I/O31
I/O0
WAIT
Figure 9.47 Burst MPX Device Connection Example
Rev. 2.00 Mar. 14, 2008 Page 366 of 1824
REJ09B0290-0200