SH7263 Datasheet, PDF(1091/1862 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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SH7263 Datasheet, PDF (1091/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

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Section 20 IEBusTM Controller (IEB)

Initial

Bit

Bit Name Value R/W Description

2

RXERTME 0

R/(W)* Receive Timing Error

Set to 1 if data is not received at the time specified by

the IEB protocol during data reception. The IEB sets

this bit and enters the wait state. This flag is enabled

only after the receive start flag (RXS) is set. If this error

occurs before the receive start flag (RXS) is set, the

IEB stops communication and enters the wait state.

This bit is not set in this case.

[Setting condition]

â¢ When a timing error occurs during data reception

[Clearing condition]

â¢ When 1 is written

1

RXEDLE 0

R/(W)* Overflow of Maximum Number of Receive Bytes in One

Frame

Indicates that the data reception has not finished within

the maximum number of bytes defined by the

communications mode because of a parity error or

overrun error causing the retransfer of data, or that

reception has not been completed because the

message length value exceeds the maximum number

of receive bytes in one frame. The IEB sets the

RXEDLE flag and enters the wait state. This flag is

enabled only after the receive start flag (RXS) is set. If

this error occurs before the receive start flag is set, the

IEB stops communication and enters the wait state.

This bit is not set in this case.

[Setting condition]

â¢ When the reception has not been completed within

the maximum number of bytes defined by

communications mode.

[Clearing condition]

â¢ When 1 is written

Rev. 2.00 Mar. 14, 2008 Page 1057 of 1824

REJ09B0290-0200

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