SH7263 Datasheet, PDF (229/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
7.3.3 Break Data Register (BDR)
BDR is a 32-bit readable/writable register. The control bits CD[1:0] and CP[1:0] in the break bus
cycle register (BBR) select one of the three data buses for a break condition.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
15 14 13 12 11 10
BD15 BD14 BD13 BD12 BD11 BD10
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W
9
BD9
0
R/W
8
BD8
0
R/W
7
BD7
0
R/W
6
BD6
0
R/W
5
BD5
0
R/W
4
BD4
0
R/W
3
BD3
0
R/W
2
BD2
0
R/W
1
BD1
0
R/W
0
BD0
0
R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BD31 to BD0 All 0
R/W Break Data Bits
Store data which specifies a break condition.
When the C bus is selected by BBR, specify the break
data on MDB in bits BD31 to BD0.
When the internal CPU bus (I bus) is selected by BBR,
specify an ICDB address in bits BD31 to BD0.
When the internal DMA bus (I bus) is selected by BBR,
specify an IDDB address in bits BD31 to BD0.
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the
word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0.
Rev. 2.00 Mar. 14, 2008 Page 195 of 1824
REJ09B0290-0200