SH7263 Datasheet, PDF (224/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
Access
control
Internal bus (I bus)
Internal Internal
DMA bus CPU bus
IDDB IDAB ICDB ICAB
CPU bus (C bus)
CPU
CPU
memory instruction
access bus fetch bus
MDB MAB FAB
Access
comparator
Address
comparator
Data
comparator
Channel 0
Access
comparator
Address
comparator
Data
comparator
Channel 1
Control
BBR_0
BAR_0
BAMR_0
BDR_0
BDMR_0
Internal
CPU bus
BBR_1
BAR_1
BAMR_1
BDR_1
BDMR_1
BRCR
[Legend]
BBR: Break bus cycle register
BAR: Break address register
BAMR: Break address mask register
BDR: Break data register
BDMR: Break data mask register
BRCR: Break control register
User break interrupt request
UBCTRG pin output
Figure 7.1 Block Diagram of UBC
Rev. 2.00 Mar. 14, 2008 Page 190 of 1824
REJ09B0290-0200