SH7263 Datasheet, PDF (1056/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
(7) Parity bit
The parity bit is used to confirm that transfer data occurs with no errors.
The parity bit is added to respective data of the master address, slave address, control, message
length, and data bits.
Even parity is used. When the number of bits having the value 1 is odd, the parity bit is 1. When
the number of bits having the value 1 is even, the parity bit is 0.
(8) Acknowledge bit
In normal communications (single unit to single unit communications), the acknowledge bit is
added in the following positions to confirm that data is correctly accepted.
• At the end of the slave address field
• At the end of the control field
• At the end of the message length field
• At the end of the data field
The acknowledge bit is defined below.
• 0: indicates that the transfer data is acknowledged. (ACK)
• 1: indicates that the transfer data is not acknowledged. (NAK)
Note that the acknowledge bit is ignored in the case of broadcast communications.
(a) Acknowledge bit at the End of the Slave Address Field
The acknowledge bit at the end of the slave address field becomes NAK in the following cases and
transfer is stopped.
• When the parity of the master address or slave address bits is incorrect
• When a timing error (an error in bit format) occurs
• When there is no slave unit
Rev. 2.00 Mar. 14, 2008 Page 1022 of 1824
REJ09B0290-0200