SH7263 Datasheet, PDF (291/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
31 to 22
Bit Name
⎯
Initial
Value
All 0
21
SZSEL
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W MPX-I/O Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BCR are specified as 11. This bit is
valid only when area 5 is specified as MPX-I/O.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus width
selected by A14 or A21 are summarized below.
SZSEL A14
A21
Bus Width
0
0
Not affected 8 bits
0
1
Not affected 16 bits
1
Not affected 0
8 bits
1
Not affected 1
16 bits
20
MPXW
0
R/W MPX-I/O Interface Address Wait
This bit setting is valid only when area 5 is specified as
MPX-I/O. Specifies the address cycle insertion wait for
MPX-I/O interface.
0: Inserts no wait cycle
1: Inserts 1 wait cycle
BAS
0
R/W SRAM with Byte Selection Byte Access Select
This bit setting is valid only when area 5 is specified as
SRAM with byte selection.
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read access cycle
and asserts the RD/WR signal at the write timing.
19
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 257 of 1824
REJ09B0290-0200