SH7263 Datasheet, PDF (423/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.3 Register Descriptions
The DMAC has the registers listed in table 10.2. There are four control registers and three reload
registers for each channel, and one common control register is used by all channels. In addition,
there is one extension resource selector per two channels. Each channel number is expressed in the
register names, as in SAR_0 for SAR in channel 0.
Table 10.2 Register Configuration
Channel
0
1
Register Name
Abbreviation R/W Initial Value
DMA source address SAR0
register_0
R/W H'00000000
DMA destination
address register_0
DAR0
R/W H'00000000
DMA transfer count
register_0
DMA channel control
register_0
DMATCR0
CHCR0
R/W H'00000000
R/W*¹ H'00000000
DMA reload source
address register_0
RSAR0
R/W H'00000000
DMA reload destination RDAR0
address register_0
R/W H'00000000
DMA reload transfer
count register_0
RDMATCR0 R/W H'00000000
DMA source address SAR1
register_1
R/W H'00000000
DMA destination
address register_1
DAR1
R/W H'00000000
DMA transfer count
register_1
DMA channel control
register_1
DMATCR1
CHCR1
R/W H'00000000
R/W*¹ H'00000000
DMA reload source
address register_1
RSAR1
R/W H'00000000
DMA reload destination RDAR1
address register_1
R/W H'00000000
DMA reload transfer
count register_1
RDMATCR1 R/W H'00000000
Address
Access
Size
H'FFFE1000 16, 32
H'FFFE1004 16, 32
H'FFFE1008 16, 32
H'FFFE100C 8, 16, 32
H'FFFE1100 16, 32
H'FFFE1104 16, 32
H'FFFE1108 16, 32
H'FFFE1010 16, 32
H'FFFE1014 16, 32
H'FFFE1018 16, 32
H'FFFE101C 8, 16, 32
H'FFFE1110 16, 32
H'FFFE1114 16, 32
H'FFFE1118 16, 32
Rev. 2.00 Mar. 14, 2008 Page 389 of 1824
REJ09B0290-0200