SH7263 Datasheet, PDF (92/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
Instruction Formats
m format
15
0
xxxx mmmm xxxx xxxx
nm format
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
Source
Operand
Destination
Operand
Example
mmmm: Register Control register or LDC Rm,SR
direct
system register
mmmm: Register
indirect with post-
increment
Control register or LDC.L @Rm+,SR
system register
mmmm: Register —
indirect
JMP @Rm
mmmm: Register
indirect with pre-
decrement
R0 (Register direct) MOV.L @-Rm,R0
mmmm: PC relative —
using Rm
BRAF Rm
mmmm: Register nnnn: Register
direct
direct
ADD Rm,Rn
mmmm: Register nnnn: Register
direct
indirect
MOV.L Rm,@Rn
mmmm: Register MACH, MACL
indirect with post-
increment (multiply-
and-accumulate)
MAC.W @Rm+,@Rn+
nnnn*: Register
indirect with post-
increment (multiply-
and-accumulate)
mmmm: Register
indirect with post-
increment
nnnn: Register
direct
MOV.L @Rm+,Rn
mmmm: Register
direct
nnnn: Register
indirect with pre-
decrement
MOV.L Rm,@-Rn
mmmm: Register nnnn: Indexed
direct
register indirect
MOV.L
Rm,@(R0,Rn)
mmmmdddd:
Register indirect
with displacement
R0 (Register direct) MOV.B
@(disp,Rm),R0
Rev. 2.00 Mar. 14, 2008 Page 58 of 1824
REJ09B0290-0200