SH7263 Datasheet, PDF (1224/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.3 Register Descriptions
Table 24.2 shows the FLCTL register configuration.
Table 24.2 Register Configuration of FLCTL
Register Name
Common control register
Command control register
Abbreviation R/W
FLCMNCR R/W
FLCMDCR R/W
Initial Value
H'0000 0000
H'0000 0000
Command code register
FLCMCDR R/W H'0000 0000
Address register
FLADR
R/W H'0000 0000
Address register 2
FLADR2
R/W H'0000 0000
Data register
FLDATAR
R/W H'0000 0000
Data counter register
FLDTCNTR R/W H'0000 0000
Interrupt DMA control register FLINTDMACR R/W H'0000 0000
Ready busy timeout setting
register
Ready busy timeout counter
FLBSYTMR
FLBSYCNT
R/W H'0000 0000
R
H'0000 0000
Data FIFO register
FLDTFIFO R/W H'xxxx xxxx
Control code FIFO register FLECFIFO R/W H'xxxx xxxx
Transfer control register
FLTRCR
R/W H'00
Address
H'FFFF F000
H'FFFF F004
Access
Size
32
32
H'FFFF F008 32
H'FFFF F00C 32
H'FFFF F03C 32
H'FFFF F010 32
H'FFFF F014 32
H'FFFF F018 32
H'FFFF F01C 32
H'FFFF F020 32
H'FFFF F050 32
H'FFFF F060 32
H'FFFF F02C 8
Rev. 2.00 Mar. 14, 2008 Page 1190 of 1824
REJ09B0290-0200