SH7263 Datasheet, PDF (1334/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
Initial
Value R/W Description
9
ACLRM
0
R/W Auto Buffer Clear Mode
0: Disabled
1: Enabled (all buffers are initialized)
8
SQCLR
ACLRM = 1 should not be set for the pipe which has
been selected by the CURPIPE bits in
CFIFOSEL/DnFIFOSEL.
0
R/W*¹ Toggle Bit Clear*²*³
0: Invalid
7
SQSET
1: Specifies DATA0
0
R/W*¹ Toggle Bit Set*²*³
0: Invalid
1: Specifies DATA1
6
SQMON
0
R
Toggle Bit Confirmation
0: DATA0
1: DATA1
5 to 2 ⎯
All 0 R
Reserved
1, 0
PID
These bits are always read as 0. The write value
should always be 0.
00
R/W Response PID*³
00: NAK response
01: BUF response (depending on the buffer state)
10: STALL response
11: STALL response
When the host controller function is selected and PID
is not set to BUF, no token is issued. If a transfer
error is detected, the controller sets the PID bits to
end the transfer.
Notes: 1. Reading of 0 and writing of 1 are valid.
2. If the SQCLR and SQSET bits in this register and DCPCTR are being used to change
the data PID sequence toggle bit for several pipes in succession, an access cycle of
120 ns and 5- or more bus clock cycles is required.
3. The SQCLR bit and SQSET bits should not be set to 1 at the same time. Before
operating either bit, PID = NAK should be set. If isochronous transfer is set for the
transfer type (TYPE = 11), writing to the SQSET bit is invalid.
Rev. 2.00 Mar. 14, 2008 Page 1300 of 1824
REJ09B0290-0200