SH7263 Datasheet, PDF (873/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
Initial
Bit
Bit Name Value R/W Description
5
RDRF
0
R/W Receive Data Full
[Clearing conditions]
• When 0 is written in RDRF after reading RDRF = 1
• When ICDRR is read
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
4
NACKF
0
R/W No Acknowledge Detection Flag
[Clearing condition]
• When 0 is written in NACKF after reading NACKF
=1
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
3
STOP
0
R/W Stop Condition Detection Flag
[Clearing condition]
• When 0 is written in STOP after reading STOP = 1
[Setting conditions]
• When a stop condition is detected after frame
transfer is completed
Rev. 2.00 Mar. 14, 2008 Page 839 of 1824
REJ09B0290-0200