SH7263 Datasheet, PDF (1301/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.16 Interrupt Status Register 0 (INTSTS0)
INTSTS0 is a register that is used to confirm interrupt statuses.
This register is initialized by a power-on reset or a software reset. By a USB bus reset, the DVSQ2
to DVSQ0 bits are initialized.
Bit: 15 14 13 12 11 10 9
8
7
VBINT RESM SOFR DVST CTRT BEMP NRDY BRDY VBSTS
Initial value: 0
0
0
0
0
0
0
0
*³
R/W: R/W*¹ R/W*¹ R/W*¹ R/W*¹ R/W*¹ R
R
R
R
6
5
4
DVSQ[2:0]
*⁴
*⁴
*⁴
RRR
3
VALID
0
R/W*¹
2
1
0
CTSQ[2:0]
0
0
0
R
R
R
Initial
Bit
Bit Name
Value R/W Description
15
VBINT
0
R/W*¹ VBUS Interrupt Status*²
0: VBUS interrupts not generated
1: VBUS interrupts generated
14
RESM
0
R/W*¹ Resume Interrupt Status*²
0: Resume interrupts not generated
1: Resume interrupts generated
13
SOFR
0
R/W*¹ Frame Number Refresh Interrupt Status*²
0: SOF interrupts not generated
1: SOF interrupts generated
12
DVST
0
R/W*¹ Device State Transition Interrupt Status*²
0: Device state transition interrupts not generated
1: Device state transition interrupts generated
11
CTRT
0
R/W*¹ Control Transfer Stage Transition Interrupt Status*²
0: Control transfer stage transition interrupts not
generated
1: Control transfer stage transition interrupts
generated
10
BEMP
0
R
Buffer Empty Interrupt Status
This bit is cleared when all of the bits in BEMPSTS
are cleared.
0: BEMP interrupts not generated
1: BEMP interrupts generated
Rev. 2.00 Mar. 14, 2008 Page 1267 of 1824
REJ09B0290-0200