SH7263 Datasheet, PDF (242/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
(3) Break Condition Specified for I Bus Data Access Cycle
(Example 3-1)
• Register specifications
BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0194, BAR_1= H'00055555,
BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F,
BRCR = H'00000000
<Channel 0>
Address: H'00314156, Address mask: H'00000000
Bus cycle: Internal CPU bus/instruction fetch/read (operand size is not included in the
condition)
<Channel 1>
Address: H'00055555, Address mask: H'00000000
Data:
H'00000078, Data mask: H'0000000F
Bus cycle: Internal DMA bus/data access/write/byte
On channel 0, the setting of the internal CPU bus/instruction fetch is ignored.
On channel 1, a user break occurs when the DMAC writes byte data H'7x in address
H'00055555 on the internal DMA bus (access via the internal CPU bus does not generate a
user break).
Rev. 2.00 Mar. 14, 2008 Page 208 of 1824
REJ09B0290-0200