SH7263 Datasheet, PDF (1474/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
27.2.5 SRC Control Register (SRCCTRL)
SRCCTRL is a 16-bit readable/writable register that enables/disables the SRC module operation,
enables/disables the interrupt requests, and specifies flush processing, clear processing of the
internal work memory, and the input and output sampling rates.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- SRCEN -
EEN FL
CL
IFS[3:0]
-
-
-
OFS
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R R/W R/W R/W R/W R/W R/W R/W R
R
R R/W
Initial
Bit
Bit Name Value R/W Description
15 to 13 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
12
SRCEN
0
R/W SRC Module Enable
Enables/disables the SRC module operation. Writing
1 while SRCEN = 0 clears the internal work memory.
0: Disables the SRC module operation.
1: Enables the SRC module operation.
Note: When SRCEN = 1, do not change the settings
of the following bits.
Register
Bit
Bit Name
SRCIDCTRL
9
IED
SRCODCTRL 10, 9
OCH, OED
SRCCTRL
7 to 4, 0
IFS[3:0], OFS
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1440 of 1824
REJ09B0290-0200