SH7263 Datasheet, PDF (1057/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
(b) Acknowledge bit at the End of the Control Field
The acknowledge bit at the end of the control field becomes NAK in the following cases and
transfer is stopped.
• When the parity of the control bits is incorrect
• When the bit 3 of the control bits is 1 (data write) although the slave receive buffer* is not
empty
• When the control bits are set to data read (H'3, H'7) although the slave transmit buffer* is
empty
• When another unit which locked the slave unit requests H'3, H'6, H'7, H'A, H'B, H'E, or H'F in
the control bits although the slave unit has been locked
• When the control bits are the locked address read (H'4, H'5) although the unit is not locked
• When a timing error occurs
• When the control bits are undefined
Note: See section 20.1.3 (1), Slave Status Read (Control Bits: H'0, H'6).
(c) Acknowledge Bit at the End of the Message Length Field
The acknowledge bit at the end of the message length field becomes NAK in the following cases
and transfer is stopped.
• When the parity of the message length bits is incorrect
• When a timing error occurs
(d) Acknowledge Bit at the End of the Data Field
The acknowledge bit at the end of the data field becomes NAK in the following cases and transfer
is stopped.
• When the parity of the data bits is incorrect*
• When a timing error occurs after the previous transfer of the acknowledge bit
• When the receive buffer becomes full and cannot accept further data*
Note: * In this case, the data field is transferred repeatedly until the number of data reaches the
maximum number of transfer bytes if the number of data does not exceed the
maximum number of transfer bytes in one frame.
Rev. 2.00 Mar. 14, 2008 Page 1023 of 1824
REJ09B0290-0200